Floating point division systems and methods continue to be of interest in the art of computer processor design. Without floating point division, even the most capable current computer processors could typically take 8 to 32 times more time to perform a routine division operation. Using less powerful modern processors, that time could increase as much as one thousand times.
The Sweeny, Robinson and Tocher (SRT) floating point division method is widely used today to perform floating point division in commercial processors, including microprocessors. The SRT method is relatively easy to implement and can calculate more than one digit of the answer for each computation cycle. However, to achieve greater speeds using existing SRT methods, the size of a SRT component, the Quotient Selection Table (QST), needs to increase exponentially. Thus, according to the present art, an increase in SRT speed also leads to an exponential increase in the need for memory.
What is needed therefore, is a more efficient SRT system and method that can yield increased floating point divisions speeds.